(1) Field of the Invention
The invention relates to semiconductor devices and circuit fabrication. More specifically, the invention relates to integrated circuits that include structures to protect the integrated circuits against various types of damages.
(2) Background of the Invention
Often semiconductor dies are subjected to mechanical agents (forces) that are likely to damage the dies. Some of these forces are surface forces that may arise, for example, when semiconductor dies are packaged. Moreover, packages, which are not completely rigid, transmit some of the external forces to the die. These forces cause delamination of various structures located at the top of the dies such as soft and hard passivation layers as well as top layer metal lines. Delamination allows moisture and other impurities to penetrate the semiconductor die.
FIG. 1 illustrates a top view of die 100. Die 100 includes die active area 102. Near edges 106 of die active area 102 are small isolated metal interconnect lines (interconnection metallization) 104 formed in the top metal layer also known as the terminal metal layer. The metal interconnect lines typically route signals on die 100. One current integrated circuit chip technology utilizes up to five layers of interconnect, referenced by M1, M2, M3, M4, and M5. In such a scheme, the terminal metal layer is M5. Lines 104 are portions of signal lines that are routed in lower layers of metal (not shown) found beneath terminal metal layer M5. Lines 104 have been shown to fail mechanically when the dies are packaged or when the packaged dies are subjected to temperature cycling during reliability testing. It is desired to protect the above-mentioned lines against the agents that damage these lines.
The invention provides in one embodiment thereof an integrated circuit. The integrated circuit includes a first interconnection metallization layer formed upon a substrate. The integrated circuit further includes a second interconnection metallization layer formed upon the first interconnection metallization layer. The second interconnection metallization layer has formed therein at least one signal line coupled to the first interconnection metallization layer. The second interconnection metallization layer has formed therein at least one protective structure that surrounds the at least one signal line.